1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory device and, more particularly, to a method of manufacturing a DRAM having a stacked capacior of a hemispherical grained (HSG) type (predetermined annealing is applied on an amorphous silicon film pattern to convert it into a polysilicon film pattern and the surface of the polysilicon film pattern into a hemispherical gained (HSG) surface to form a storage node electrode).
2. Description of the Prior Art
In recent years, semiconductor memory devices continue to shrink in feature size and increase in integration density. Particularly, the integration density of DRAMs has quadrupled every three years, i.e., 64 Mbits, 256 Mbits, and 1 Gbit. Along with this tendency of higher integration, the cell size of memory cells is also reduced. For a 64-Mbit cell, the cell size is about 1.0 .mu.m.sup.2, and for a 256-Mbit cell, the cell size is about 0.55 .mu.m.sup.2. Such cell size reduction makes it difficult to ensure a prescribed cell capacitance. For this reason, the main stream is a stacked capacitor having a three-dimensional storage node electrode. For the three-dimensional storage node electrode, the bit line is arranged under the capacitor (COB structure). In a memory cell having such a COB structure, a BPSG film is often used as an insulating interlayer between the bit line and the capacitor.
The present inventor has filed Japanese Unexamined Patent Publication No. 3-272165 which discloses a technique of converting the exposed two-dimensional upper and side surfaces of the storage node electrode into surfaces with microstructures to increase the cell capacitance. The storage node electrode of the stacked capacitor according to this prior art is formed in the following manner. The surface of an amorphous silicon film pattern is processed at a temperature slightly higher than the phase transition temperature from amorphous silicon to polysilicon, whereby the amorphous silicon film pattern is converted into a polysilicon film pattern. Simultaneously, the surface of the polysilicon film pattern is covered with hemispherical grains (HSG) to form a storage node electrode.
In formation of a DRAM memory cell having an HSG stacked capacitor, it is essential to remove the native oxide film on the surface of the amorphous silicon film pattern before the HSG process at the above temperature. The native oxide film is removed using dilute hydrofluoric acid, as disclosed in Japanese Unexamined Patent Publication No. 5-67730 filed by the present inventor.
The memory cell having the COB structure in which the storage node electrode is formed on an insulating interlayer consisting of a BPSG film has the following disadvantages.
When the amorphous silicon film pattern as a prospective storage node electrode is directly formed on the BPSG film, those portions of the BPSG film which are not covered with the amorphous silicon film pattern are also etched in the dilute hydrofluoric acid process of removing the native oxide film on the amorphous silicon film pattern. The BPSG film forms an undercut at the bottom portion of the amorphous silicon film pattern, and the mechanical strength of the amorphous silicon film pattern or the HSG-converted polysilicon film pattern (i.e., the storage node electrode) suffers. For this reason, these film patterns may easily break, resulting in poor workability in subsequent manufacturing processes. Even when the surface of the BPSG film is covered with a silicon oxide film (LTO film) formed by low-temperature chemical vapor deposition such as APCVD, such a degradation in mechanical strength can hardly be suppressed (although the degree of undercut is relaxed to some extent).
The degradation in mechanical strength can be easily suppressed if the surface of the BPSG film is covered with a silicon nitride film (which is sufficiently thicker than a capacitive dielectric film) or a silicon oxide film (HTO film) formed by high-temperature chemical vapor deposition. In these cases, however, the threshold value (V.sub.TH) of the n-channel MOS transistor (transfer transistor) constituting the memory cell varies to a small value to result in hold failures. The reason why this phenomenon takes place when the surface of the BPSG film is covered with a silicon nitride film is as follows. In the hydrogen alloy process as a postprocess, hydrogen cannot easily reach the interface between the gate oxide film and the p-type silicon substrate of the n-channel MOS transistor because of the presence of the sufficiently thick silicon nitride film, and interfacial charges trapped at the interfacial level of the interface can hardly be decreased. When the surface of the BPSG film is to be covered with an HTO film, the n-channel MOS transistor is held at a temperature of about 800.degree. C. for a long time during formation of the HTO film. As a result, a short channel effect becomes prominent by redistribution of the impurity in n-type source and drain regions, thus making the threshold value V.sub.TH smaller than the design target value. The HTO film is formed by high-temperature chemical vapor deposition at about 800.degree. C., i.e., low-pressure chemical vapor deposition (LPCVD) using monosilane (SiH.sub.4) and nitrous oxide (N.sub.2 O). Although the actual HTO film deposition time itself is relatively short, the entire process takes a time of about three hours including the time for inserting/extracting the structure into/from the film forming apparatus.